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| this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 0.4 / sep. 2006 1 hy5ps561621a(l)fp 256mb ddr2 sdram hy5ps561621a(l)fp
rev. 0.4 / sep. 2006 2 1 1 hy5ps561621a(l)fp revision history rev. history draft date 0.1 initial data sheet release. june. 2005 0.2 removed all contents on x4/8 org. updated idd spec. oct. 2005 0.3 removed improper note in odt dc spec. july 2006 0.4 timing parameters table modified sep. 2006 rev. 0.4 / sep. 2006 3 1 1 hy5ps561621a(l)fp contents 1. description 1.1 device features and ordering information 1.1.1 key feaures 1.1.2 ordering information 1.1.3 ordering frequency 1.2 pin configuration 1.3 pin description 2. maximum dc ratings 2.1 absolute maximum dc ratings 2.2 operating temperature condition 3. ac & dc operating conditions 3.1 dc operating conditions 5.1.1 recommended dc operating conditions(sstl_1.8) 5.1.2 odt dc electrical characteristics 3.2 dc & ac logic input levels 3.2.1 input dc logic level 3.2.2 input ac logic level 3.2.3 ac input test conditions 3.2.4 differential input ac logic level 3.2.5 differential ac output parameters 3.3 output buffer levels 3.3.1 output ac test conditions 3.3.2 output dc current drive 3.3.3 ocd default chracteristics 3.4 idd specifications & measurement conditions 3.5 input/output capacitance 4. ac timing specifications 5. package dimensions rev. 0.4 / sep. 2006 4 1 1 hy5ps561621a(l)fp 1. description 1.1 device features & ordering information 1.1.1 key features ? vdd ,vddq =1.8 +/- 0.1v ? all inputs and outputs are compatible with sstl_18 interface ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous-data transaction aligne d to bidirectional data strobe (dqs, dqs ) ? differential data strobe (dqs, dqs ) ? data outputs on dqs, dqs edges when read (edged dq) ? data inputs on dqs centers when write(centered dq) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm mask write data-in at the both risi ng and falling edges of the data strobe ? all addresses and control inputs except data, data stro bes and data masks latched on the rising edges of the clock ? programmable cas latency 3, 4, 5 and 6 supported ? programmable additive latency 0, 1, 2, 3, 4 and 5 supported ? programmable burst length 4 / 8 with both nibble sequential and interleave mode ? internal four bank operations with single pulsed ras ? auto refresh and self refresh supported ? tras lockout supported ? 8k refresh cycles /64ms ? jedec standard 84ball fbga(x16) ? full strength driver option controlled by emrs ? on die termination supported ? off chip driver impedance adjustment supported ? self-refresh high temperature entry ? partial array self refresh support ordering information part no. organization package hy5ps561621a(l)fp-x* 16mx16 lead free** note: 1. -x* is the speed bin, refer to the operation frequency table for complete part no. 2. hynix lead-free products are compliant to rohs. operating frequency speed bin tck(ns) cl trcd trp unit e3 5333 clk c4 3.75 4 4 4 clk y5 3555 clk s5 2.5 5 5 5 clk rev. 0.4 / sep. 2006 5 1 1 hy5ps561621a(l)fp 1.2 pin configuratio n & address table 16mx16 ddr2 pin configuration(top view: see balls through package) 3 vss udm vddq dq11 vss we ba1 a1 a5 a9 nc 2 nc vssq dq9 vssq vref cke ba0 a10 a3 a7 a12 1 vdd dq14 vddq dq12 vddl nc vss vdd a b c d j k l m n p r 7 vssq udqs vddq dq10 vssdl ras cas a2 a6 a11 nc 8 udqs vssq dq8 vssq ck ck cs a0 a4 a8 nc 9 vddq dq15 vddq dq13 vdd odt vdd vss vss ldm vddq dq3 nc vssq dq1 vssq vdd dq6 vddq dq4 e f g h vssq ldqs vddq dq2 ldqs vssq dq0 vssq vddq dq7 vddq dq5 row and column address table items 16mx16 # of bank 4 bank address ba0, ba1 auto precharge flag a10/ap row address a0 - a12 column address a0-a8 page size 1 kb rev. 0.4 / sep. 2006 6 1 1 hy5ps561621a(l)fp 1.3 pin description pin type description ck, ck input clock: ck and ck are differential clock in puts. all address and contro l input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is refer- enced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates intern al clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all banks idle), or active power down (row active in any bank). cke is synchronous for power down entry and ex it, and for self refres h entry. cke is asyn- chronous for self refresh exit. after v ref has become stable during the power on and initial- ization sequence, it must be maintained for pr oper operation of the cke receiver. for proper self-refresh entry and exit, v ref must be maintained to this inpu t. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power down. input buffers, excluding cke are disabled during self refresh. cs input chip select : all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. odt input on die termination control : odt(registered high ) enables on die termination resistance inter- nal to the ddr2 sdram. when enabled, odt is only applied to dq, dqs, dqs , rdqs, rdqs , and dm signal for x4,x8 configur ations. for x16 configuration od t is applied to each dq, udqs/ udqs .ldqs/ldqs , udm and ldm signal. the odt pin will be ignored if the extended mode register(emrs(1)) is programmed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm (ldm, udm) input input data mask : dm is an input mask signal fo r write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs, although dm pins are input only , the dm loading matches the dq and dqs load- ing. for x8 device, the function of dm or rdqs/ rdqs is enabled by emrs command. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied(for 256mb and 512mb, ba2 is not applied). bank address also deter- mines if the mode register or extended mode regi ster is to be accessed during a mrs or emrs cycle. a0 -a15 input address inputs: provide the row address for ac tive commands, and the column address and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0-ba2. the address inputs also provide the op code during mode register set commands. dq input/ output data input / output : bi-directional data bus rev. 0.4 / sep. 2006 7 1 1 hy5ps561621a(l)fp dqs, (dqs) (udqs),(udqs ) (ldqs),(ldqs ) (rdqs),(rdqs ) input/ output data strobe : output with read data, input with write data. edge aligned with read data, cen- tered in write data. for the x16, ldqs correspo nd to the data on dq0~dq7; udqs corresponds to the data on dq8~dq15. for the x8, an rdqs option using dm pin can be enabled via the emrs(1) to simplify read timing. the data strobes dqs, ldqs, udqs, and rdqs may be used in single ended mode or paired with optional complementary signals dqs, ldqs,udqs and rdqs to provide differential pair signaling to the sy stem during both reads and wirtes. an emrs(1) control bit enables or disables all complementary data strobe signals. in this data sheet, "differential dqs signals" refe rs to any of the following with a10 = 0 of emrs(1) x16 ldqs/ldqs and udqs/udqs "single-ended dqs signals" refers to any of the following with a10 = 1 of emrs(1) x16 ldqs and udqs nc no connect : no internal elec trical connection is present. v ddq supply dq power supply: 1.8v +/- 0.1v vssq supply dq ground v ddl supply dll power supply : 1.8v +/- 0.1v v ssdl supply dll ground vdd supply power supply : 1.8v +/- 0.1v v ss supply ground v ref supply reference voltage for inputs for sstl interface. pin type description rev. 0.4 / sep. 2006 8 1 1 hy5ps561621a(l)fp 2. maximum dc ratings 2.1 absolute maxi mum dc ratings 2.2 operating temp erature condition symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1 vddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1 vddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent dama ge to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximu m rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the denter/top side of the dram. for the measurement conditions. please refer to jesd51-2 standard. symbol parameter rating units notes toper operating temperature 0 to 95 c 1,2 1. operating temperature is the case surface temperature on t he center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 2. at toper 85~95 , double refresh rate(trefi: 3.9us) is required, and to enter the self refresh mode at this temperature range it must be reguired an emrs command to change iself refresh rate. rev. 0.4 / sep. 2006 9 1 1 hy5ps561621a(l)fp 3. ac & dc operating conditons 3.1 dc operating conditions 3.1.1 recommended dc operating conditions (sstl_1.8) 3.1.2 odt dc electrical characteristics symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v 1 vddl supply voltage for dll 1.7 1.8 1.9 v 1,2 vddq supply voltage for output 1.7 1.8 1.9 v 1,2 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 3,4 vtt termination voltage vref-0.04 vref vref+0.04 v 5 1. min. typ. and max. values increase by 100mv for c3 ( ddr2-533 3-3-3) speed option. 2. vddq tracks with vdd,vddl tracks with vdd. ac parameters are measured with vdd,vddq and vdd. 3. the value of vref may be selected by the user to provide optim um noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting devic e and vref is expected to track variations in vddq 4. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 5. vtt of transmitting device must track vref of receiving device. parameter/condition symbol min nom max units notes rtt effective impedance value for emrs(a6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,1; 50 ohm rtt3(eff) 40 50 60 ohm 1 deviation of vm with respect to vddq/2 delta vm -6 +6 % 1 note 1. test condition for rtt measurements measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac)) and i(v il (ac)) respectively. v ih (ac), v il (ac), and vddq values defined in sstl_18 measurement definition for vm : measurement vo ltage at test pin(mid point) with no load. rtt(eff) = v ih (ac) - v il (ac) i( v ih (ac) ) - i( v il (ac) ) delta vm = 2 x vm vddq x 100% - 1 rev. 0.4 / sep. 2006 10 1 1 hy5ps561621a(l)fp 3.2 dc & ac logic input levels 3.2.1 input dc logic level 3.2.2 input ac logic level 3.2.3 ac input test conditions note: 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switch ing from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. symbol parameter min. max. units notes v ih (dc) dc input logic high vref + 0.125 vddq + 0.3 v v il (dc) dc input logic low - 0.3 vref - 0.125 v symbol parameter ddr2 400,533 ddr2 667,800 units notes min. max. min. max. v ih (ac) ac input logic high vref + 0.250 - vref + 0.200 - v v il (ac) ac input logic low - vref - 0.250 - vref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ref v swing(max) delta tr delta tf v ih(dc) min v il(dc) max v il(ac) max v ss rising slew = delta tr v ih(ac) min - v ref v ref - v il(ac) max delta tf falling slew = < figure : ac input test signal waveform> rev. 0.4 / sep. 2006 11 1 1 hy5ps561621a(l)fp 3.2.4 differential input ac logic level 3.2.5 differential ac output parameters symbol parameter min. max. units notes v id (ac) ac differential input voltage 0.5 vddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 1. vin(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. vid(dc) specifies the input differential voltage |vtr -vcp | re quired for switching, where vtr is the true input (such as ck , dqs, ldqs or udqs) level and vc p is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to vih(dc) - v il(dc). note: 1. vid(ac) specifies the input differential voltage |vtr -vcp | required for switching, where vtr is the true input signal (suc h as ck, dqs, ldqs or udqs) and vcp is the complementary inpu t signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih(ac) - v il(ac). 2. the typical value of vix(ac) is expected to be about 0.5 * vddq of the transmitting device and vix(ac) is expected to track variations in vddq . vix(ac) indicates the voltage at which differential input signals must cross. symbol parameter min. max. units notes v ox (ac) ac differential cr oss point voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 1 note: 1. the typical value of v ox(ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox(ac ) is expected to track variations in vddq . v ox(ac) indicates the voltage at whitch differential output signals must cross. v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels > rev. 0.4 / sep. 2006 12 1 1 hy5ps561621a(l)fp 3.3 output buffer characteristics 3.3.1 output ac test conditions 3.3.2 output dc current drive 3.3.3 ocd defalut characteristics symbol parameter sstl_18 class ii units notes v otr output timing measurement reference level 0.5 * v ddq v1 1. the vddq of the device under test is referenced. symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh(dc) and i ol(dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting t he desired driver operating point (see section 3.3) along a 21 ohm load line to define a convenient driver current for measurement. description parameter min nom max unit notes output impedance - - - ohms 1 output impedance step size for ocd calibration 0 1.5 ohms 6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output slew rate sout 1.5 - 5 v/ns 1,4,5,6,7,8 rev. 0.4 / sep. 2006 13 1 1 hy5ps561621a(l)fp note 1. absolute specifications ( to p e r ; vdd = +1.8v 0.1 v, vddq = +1.8v 0.1v) 2. impedance measurement condition for output source dc cu rrent: vddq=1.7v; vout=1420mv; (vout-vddq)/ioh must be less than 23.4 ohms for values of vout between vddq an d vddq-280mv. impedance measurement condition for output sink dc current: vddq = 1.7v; vout = 280mv; vout/iol must be less than 23.4 ohms for values of vout between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull-d n, both are measured at sa me temperature and voltage. 4. slew rate measured from vil(ac) to vih(ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. 6. this represents the step size when th e ocd is near 18 ohms at nominal conditions across all process co rners/variations and represents only the dram uncertainty. a 0 ohm value(no calibration) can only be achieved if the ocd impedance is 18 ohms +/- 0.75 ohms under nominal conditions. output slew rate load: 7. dram output slew rate specification applies to 400 , 533 and 667 mt/s speed bins. 8. timing skew due to dram output slew rate mis-match between dqs / dqs and associated dqs is included in tdqsq and tqhs specification. vtt 25 ohms output (vout) reference point rev. 0.4 / sep. 2006 14 1 1 hy5ps561621a(l)fp 3.4 idd specifications & test conditions idd specifications (x16) (t case : 0 to 95 o c ) notes : 1. idd6 current alues are guaranted up to tcase of 85 o c max. symbol ddr2 800 @cl5 ddr2 667 @cl5 ddr2 533 @cl4 ddr2 400 @cl3 units note idd0 85 80 75 70 ma idd1 105 100 90 80 ma idd2p 8876ma idd2q 40 35 30 25 ma idd2n 45 40 35 30 ma idd3p(f) 35 35 30 30 ma idd3p(s) 35 35 30 30 ma idd3n 60 55 50 45 ma idd4w 200 180 160 140 ma idd4r 190 150 130 120 ma idd5b 120 120 115 110 ma idd6(normal) 4444ma1 idd6(low) 2222ma1 idd7 230 220 210 200 ma rev. 0.4 / sep. 2006 15 1 1 hy5ps561621a(l)fp idd test conditions (idd values are for full operating range of voltage and temperature, notes 1-5) symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras min(idd) ; cke is high, cs is high between valid commands;address bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge curren ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are switching ; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other cont rol and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid com- mands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are sw itching;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and addr ess bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following page for det ailed timing conditions ma note: 1. vddq = 1.8 +/- 0.1v ; vdd = 1.8 +/- 0.1v (exclusively vddq = 1.9 +/- 0.1v ; vdd = 1. 9 +/- 0.1v for c3 speed grade) 2. idd specifications are tested afte r the device is properly initialized 3. input slew rate is specified by ac parametric test condition 4. idd parameters are s pecified with odt disabled. 5. data bus consists of dq, dm, dqs, dqs, rdqs, rdqs, ldqs, ldqs, udqs, and udqs. idd values must be met with all combinations of emrs bits 10 and 11. 6. definitions for idd low is defined as vin vilac(max) high is defined as vin vihac(min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cycl e (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer (o nce per clock) for dq signals not including masks or strobes. rev. 0.4 / sep. 2006 16 1 1 hy5ps561621a(l)fp for purposes of idd testing, the follo wing parameters are to be utilized detailed idd7 the detailed timings are shown below for idd7. changes will be re quired if timing parameter changes are made to the specificati on. legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all ba nk interleave read operation all banks are being interleaved at minimum t rc(idd) without violating t rrd(idd) using a burst length of 4. control and address bus inputs are stable during deselects. iout = 0ma timing patterns for 4 bank devices x4/ x8/ x16 -ddr2-400 3/3/3: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d (11 clocks) -ddr2-533 3/3/3: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d (15 clocks) -ddr2-533 4/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d (16 clocks) -ddr2-667 4/4/4: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d (19 clocks) -ddr2-667 5/5/5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d (20 clocks) speed bin (cl-trcd-trp) ddr2-800 ddr2-667 ddr2-533 ddr2-400 units 5-5-5 6-6-6 4-4-4 5-5-5 3-3-3 4-4-4 3-3-3 cl(idd) 5645 3 4 3tck t rcd(idd) 12.5 15 12 15 11.25 15 15 ns t rc(idd) 57.25 60 57 60 56.25 60 55 ns t rrd(idd)-x4/x8 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns t rrd(idd)-x16 10 10 10 10 10 10 10 ns t ck(idd) 2.5 2.5 3 3 3.75 3.75 5 ns t rasmin(idd) 45 45 45 45 45 45 40 ns t rasmax(idd) 70000 70000 70000 70000 70000 70000 70000 ns t rp(idd) 12.5 15 12 15 11.25 15 15 ns t rfc(idd)-256mb 75 75 75 75 75 75 75 ns t rfc(idd)-512mb 105 105 105 105 105 105 105 ns t rfc(idd)-1gb 127.5 127.5 127.5 127.5 127.5 127.5 127.5 ns rev. 0.4 / sep. 2006 17 1 1 hy5ps561621a(l)fp 3.5. input/output capacitance 4. electrical characteristics & ac timing specification ( 0 t case 95; v ddq = 1.8 v +/- 0.1v; v dd = 1.8v +/- 0.1v) refresh parameters ddr2 sdram speed bins and trcd, trp and trc for corresponding bin parameter symbol ddr2- 400 ddr2- 533 ddr2 667 ddr2 800 units min max min max min max input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 2.0 1.0 1.75 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 2.5 3.5 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 x 0.5 pf parameter symbol spec units refresh to active/refresh command time trfc 75 ns average periodic refresh interval trefi 0 t case 8 5 7.8 ns 85 < t case 95 3.9 ns speed ddr2-800 ddr2-667 ddr2-533 ddr2-400 units bin(cl-trcd-trp) 5-5-5 5-5-5 4-4-4 3-3-3 parameter min min min min cas latency 55 4 5tck trcd 12.5 15 15 15 ns trp 12.5 15 15 15 ns tras 45 45 45 40 ns trc 57.25 60 60 55 ns rev. 0.4 / sep. 2006 18 1 1 hy5ps561621a(l)fp timing parameters by speed grade (refer to notes for information related to this table at the following pages of this table) parameter symbol ddr2-400 ddr2-533 unit note min max min max dq output access time from ck/ck tac -600 +600 -500 +500 ps dqs output access time from ck/ck tdqsck -500 +500 -450 +450 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl,tch) - min(tcl,tch) - ps 11,12 clock cycle time, cl=x tck 5000 8000 3750 8000 ps 15 dq and dm input setup time(differential strobe) tds(base) 150 -100 - ps 6,7,8,20 dq and dm input hold time(differential strobe) tdh(base) 275 -225 - ps 6,7,8,21 dq and dm input setup time(single ended strobe) tds 25 --25 - ps 6,7,8,20 dq and dm input hold time(single ended strobe) tdh 25 --25 - ps 6,7,8,21 control & address input pulse width for each input tipw 0.6 -0.6 - tck dq and dm input pulse width for each input tdipw 0.35 -0.35 - tck data-out high-impedance time from ck/ck thz - tac max - tac max ps 18 dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps 18 dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps 18 dqs-dq skew for dqs and associated dq signals tdqsq -350 -300 ps 13 dq hold skew factor tqhs -450 -400 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching transition to associated clock edge tdqss -0.25 + 0.25 -0.25 + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck 10 write preamble twpre 0.35 - 0.35 - tck address and control input setup time tis(base) 350 -250 - ps 5,7,9,23 address and control input hold time tih(base) 475 -375 - ps 5,7,9,23 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck active to active command period trrd 7.5 -7.5 - ns 4 four activate window tfaw 37.5 -37.5 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal wr+trp - wr+trp - tck 14 internal write to read command delay twtr 10 -7.5 - ns 24 internal read to precharge command delay trtp 7.5 7.5 ns 3 rev. 0.4 / sep. 2006 19 1 1 hy5ps561621a(l)fp parameter symbol ddr2-400 ddr2-533 unit note min max min max exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck 1 exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck 1, 2 cke minimum pulse width (high and low pulse width) t cke 3 3 tck 27 odt turn-on delay t aond 2222tck odt turn-on t aon tac(min) tac(max)+ 1 tac(min) tac(max)+ 1 ns 16 odt turn-on(power-down mode) t aonpd tac(min)+2 2tck+ tac(max)+ 1 tac(min)+2 2tck+ tac(max)+ 1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns 17 odt turn-off (power-down mode) t aofpd tac(min)+2 2.5tck+ tac(max)+ 1 tac(min)+2 2.5tck+ tac(max)+ 1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih tis+tck+tih ns 15 -continue- rev. 0.4 / sep. 2006 20 1 1 hy5ps561621a(l)fp parameter symbol ddr2-667 ddr2-800 unit note min max min max dq output access time from ck/ck tac -450 +450 -400 +400 ps dqs output access time from ck/ck tdqsck -400 +400 -350 +350 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) - min(tcl, tch) - ps 11,12 clock cycle time, cl=x tck 3000 8000 2500 ps 15 dq and dm input setup time tds(base) 100 - 50 - ps 6,7,8,20 dq and dm input hold time tdh(base) 175 - 125 - ps 6,7,8,21 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance time from ck/ck thz - tac max - tac max ps 18 dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps 18 dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps 18 dqs-dq skew for dqs and associated dq signals tdqsq - 240 - 200 ps 13 dq hold skew factor tqhs - 340 - 300 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching transition to associated clock edge tdqss - 0.25 + 0.25 - 0.25 + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck 10 write preamble twpre 0.35 - 0.35 - tck address and control input setup time tis(base) 200 -175 - ps 5,7,9,22 address and control input hold time tih(base) 275 -250 - ps 5,7,9,23 read preamble trpre 0.9 1.1 0.9 1.1 tck 19 read postamble trpst 0.4 0.6 0.4 0.6 tck 19 activate to precharge command tras 45 70000 45 70000 ns 3 active to active command period for 1kb page size products trrd 7.5 -7.5 - ns 4 four activate window tfaw 37.5 - 37.5 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal wr+trp - wr+trp - tck 14 internal write to read command delay twtr 7.5 -7.5 - ns internal read to precharge command delay trtp 7.5 7.5 ns 3 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck rev. 0.4 / sep. 2006 21 1 1 hy5ps561621a(l)fp -continue- parameter symbol ddr2-667 ddr2-800 unit note min max min max exit active power down to read command txard 2 2 tck 1 exit active power down to read command (slow exit, lower power) txards 7 - al 8 - al tck 1, 2 cke minimum pulse width (high and low pulse width) t cke 3 3 tck odt turn-on delay t aond 2222tck odt turn-on t aon tac(min) tac(max) +0.7 tac(min) tac(max) +0.7 ns 6,16 odt turn-on(power-down mode) t aonpd tac(min)+2 2tck+ tac(max)+1 tac(min) +2 2tck+ tac(max)+1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max)+ 0.6 tac(min) tac(max) +0.6 ns 17 odt turn-off (power-down mode) t aofpd tac(min) +2 2.5tck+ tac(max)+1 tac(min) +2 2.5tck+ tac(max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih tis+tck +tih ns 15 rev. 0.4 / sep. 2006 22 1 1 hy5ps561621a(l)fp general notes, which may apply for all ac parameters 1. slew rate measurement levels a. output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = -500 mv and dqs - dqs = +500mv. output slew rate is guaranteed by design, bu t is not necessarily tested on each device. b. input slew rate for single ended signals is measured from dc -level to ac-level: from vil(dc) to vih(ac) for ri sing edges and from vih(dc) and vil(ac) for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck - ck = +500 mv(250mv to -500 mv for falling egdes). c. vid is the magnitude of the difference between th e input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 2. ddr2 sdram ac timing reference load the following figure represents the timing reference load used in defining the relevant timing parameters of the part. it is no t intended to be either a precise representa tion of the typical system environment nor a depiction of the actual load presented b y a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to a system e nviron- ment. manufacturers will correlate to their production test condit ions (generally a coaxial transmission line terminated at the tester electronics) . the output timing reference voltage level for single ended signal s is the crosspoint with vtt. the output timing reference volt age level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs) signal. 3. ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as shown below. 4. differential data strobe ddr2 sdram pin timings are specif ied for either single ended mode or differenti al mode depending on the setting of the emrs ?enable dqs? mode bit; timing advantages of differential mode are realized in system design . the method by which the ddr2 sdram pin timings are measured is mode dependent. in single vddq dut dq dqs dqs rdqs rdqs output v tt = v ddq /2 25 timing reference point ac timing reference load vddq dut dq dqs, dqs rdqs, rdqs output v tt = v ddq /2 25 test point slew rate test load rev. 0.4 / sep. 2006 23 1 1 hy5ps561621a(l)fp vref. in differential mode, these timing re lationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is dis abled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 k ohm resistor to insure proper operation. 5. ac timings are for linear sign al transitions. see system derating for other signal transitions. 6. these parameters guarantee device behavior, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 7. all voltages referenced to vss. 8. tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal reference/ supply voltage levels, but the related specifications and device operation are guar anteed for the full voltage range specified. t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh figure -- data input (write) timing dmin dmin dmin d d d dqs v ih (ac) v il (ac) v ih (ac) v il (ac) v ih (dc) v il (dc) v ih (dc) v il (dc) t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax figure -- data output (read) timing q qq rev. 0.4 / sep. 2006 24 1 1 hy5ps561621a(l)fp specific notes for dedicated ac parameters 1. user can choose which active power down exit timing to use via mrs(bit 12). txard is expected to be used for fast active power down exit timing. txards is expected to be used fo r slow active power down exit ti ming where a lower power value is defined by each vendor data sheet. 2. al = addi tive latency 3. this is a minimum requiremen t. minimum read to precharge timing is al + bl /2 providing the trtp and tras(min) have been satisfied. 4. a minimum of two clocks (2 * tck) is re quired irrespective of operating frequency 5. timings are guaranteed with command/add ress input slew rate of 1.0 v/ns. see system derating for other slew rate values. 6. timings are guaranteed with data, mask , and (dqs/rdqs in singled ended mode) in put slew rate of 1.0 v/ns. see system derating for other slew rate values. 7. timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. timi ngs are guaranteed for dqs signals with a differen tial slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1v/ns in single ended mode. see system derating for other slew rate values. 8. tds and tdh derating table (for ddr2- 400 / 533) 1) for all input signals the total tds(setup time) and tdh(hold ti me) required is calculated by adding the datasheet value to t he derating value listed in above table. setup(tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the firs t crossing of vih(ac)min. setup(tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref( dc) and the first crossing of vil(ac)max. if the actu al signal is always earlier than the nomi nal slew rate line between shaded ? vref( dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the actual signal is later than the nominal slew rate line any where between shaded ?vref(dc) to ac region?, the slew rate of a tangen t line to the actual signal from the ac level to dc level is u sed for derating value(see fig b.) hold(tdh) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of vil(dc) max and t he first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is define d as the slew rate between the last crossing o f vih(dc) min and the first crossing of vref(dc). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value(see fig d.) although for slow slew rates the total setup time might be nega tive(i.e. a valid input signal wi ll not have reached vih/il(ac) at the td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h 2.0 125 45 125 45 +125 +45 - - - - - - - - - - - - 1.5 83218321+83+219533---------- 1.0 00000012122424-------- 0.9 - - -11-14-11-141 -213102522 - - - - - - 0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - - 0.7 -------31-42-42-19-7-85-6176-- 0.6 ---------43-59-31-47-19-35-7-235-11 0.5 -----------74-89-62-77-50-65-38-53 0.4 - - - - - - - - - - - - -127 -140 -115 -128 -103 -116 tds, tdh derating values(all units in 'ps', note 1 applies to entire table) 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 4.0 v/ns 3.0 v/ns 0.8 v/ns dq slew rate v/ns dqs, dqs differential slew rate 2.0 v/ns 1.8 v/ns rev. 0.4 / sep. 2006 25 1 1 hy5ps561621a(l)fp time of the rising clock transition) a valid input signal is st ill required to complete the tr ansition and re ach vih/il(ac). for slew rate in between the values li sted in table x, the derating valued may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by de sign and characterization. hold(tdh) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of vil(dc) max and t he first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is define d as the slew rate between the last crossing o f vih(dc) min and the first crossing of vref(dc). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value(see fig d.) although for slow slew rates the total setup time might be nega tive(i.e. a valid input signal wi ll not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is st ill required to complete the tr ansition and re ach vih/il(ac). for slew rate in between the values li sted in table x, the derating valued may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by de sign and characterization. rev. 0.4 / sep. 2006 26 1 1 hy5ps561621a(l)fp fig. a illustration of nomi nal slew rate for tis,tds ck,dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (ac)max setup slew rate falling signal = delta tf v ih (ac)min-v ref (dc) setup slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh ck, dqs rev. 0.4 / sep. 2006 27 1 1 hy5ps561621a(l)fp fig. -b illustration of tangent line for tis,tds ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region tangent line tangent line t is , t ds ck, dqs nomial line nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] setup slew rate rising signal = tangent line[v ref (dc)-v il (ac)max] setup slew rate falling signal = delta tf t ih , t dh t is , t ds t ih , t dh rev. 0.4 / sep. 2006 28 1 1 hy5ps561621a(l)fp fig. -c illustration of nominal line for tih, tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tr nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (dc)max hold slew rate rising signal = delta tr v ih (dc)min - v ref (dc) hold slew rate falling signal = delta tf dc to v ref region delta tf ck, dqs t ih , t dh t is , t ds t ih , t dh rev. 0.4 / sep. 2006 29 1 1 hy5ps561621a(l)fp fig. -d illustration of tangent line for tih , tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf tangent line tangent line t is , t ds ck, dqs nominal line dc to v ref region nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] hold slew rate falling signal = delta tf tangent line[v ref (dc)-v il (ac)max] hold slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh rev. 0.4 / sep. 2006 30 1 1 hy5ps561621a(l)fp 9. tis and tih (input setup and hold) derating tis tih tis tih tis tih units notes 4.0 +187 +94 +217 +124 +247 +124 ps 1 3.5 +179 +89 +209 +119 +239 +149 ps 1 3.0 +167 +83 +197 +113 +227 +143 ps 1 2.5 +150 +75 +180 +105 +210 +135 ps 1 2.0 +125 +45 +155 +75 +185 +105 ps 1 1.5 +83 +21 +113 +51 +143 +81 ps 1 1.0 +0 0 +30 +30 +60 60 ps 1 0.9 -11 -14 +19 +16 +49 +46 ps 1 0.8 -25 -31 +5 -1 +35 +29 ps 1 0.7 -43 -54 -37 -53 -7 +6 ps 1 0.6 -67 -83 -37 -53 -7 -23 ps 1 0.5 -100 -125 -80 -95 -50 -65 ps 1 0.4 -150 -188 -145 -158 -115 -128 ps 1 0.3 -223 -292 -255 -262 -225 -232 ps 1 0.25 -250 -375 -320 -345 -290 -315 ps 1 0.2 -500 -500 -495 -470 -465 -440 ps 1 0.15 -750 -708 -770 -678 -740 -648 ps 1 0.1 -1250 -1125 -1420 -1095 -1065 tbd ps 1 tis tih tis tih tis tih units notes 4.0 +150 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 +163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +160 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 60 ps 1 0.9 -5 -14 +25 +16 +55 +46 ps 1 0.8 -13 -31 +17 -1 +47 +29 ps 1 0.7 -22 -54 +8 -24 +38 +6 ps 1 0.6 -34 -83 -4 -53 -26 -23 ps 1 0.5 -60 -125 -30 -95 0 -65 ps 1 0.4 -100 -188 -70 -158 -40 -128 ps 1 0.3 -168 -292 -138 -262 -108 -232 ps 1 0.25 -200 -375 -170 -345 -140 -315 ps 1 0.2 -325 -500 -295 -470 -265 -440 ps 1 0.15 -517 -708 -487 -678 -457 -648 ps 1 0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1 tis, tih derating values for ddr2 400, ddr2 533 command / address slew rate(v/ns) 2.0 v/ns ck, ck differential slew rate 1.5 v/ns 1.0 v/ns command / address slew rate(v/ns) tis, tih derating values for ddr2 667, ddr2 800 ck, ck differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns rev. 0.4 / sep. 2006 31 1 1 hy5ps561621a(l)fp 1) for all input signals the total tis(setup time) and tih(hold) ti me) required is calculated by adding the datasheet value to the derating value listed in above table. setup(tis) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup(tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than the nominal slew rate for line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for der- ating value(see fig b.) hold(tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the fir st cross- ing of v ref (dc). hold(tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc). if the actual signal signal is always later than the nominal slew rate line between shaded ?dc to v ref (dc) region?, use nominal slew rate for derating value(see fig.c) if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value(see fig d.) although for slow rates the total setup time might be ne gative(i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is st ill required to complete the transition and reach v ih/il (ac). for slew rates in between the values listed in table, the derating values may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by de sign and characterization. 10. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter , but system performance (bus turnaround) will degrade accordingly. 11. min ( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the devi ce (i.e. this value can be greater than the minimum specification limits for t cl and t ch). for example, t cl and t ch are = 50% of the period, less the half period jitter ( t jit(hp)) of the clock source, and less the half period jitter due to crosst alk ( t jit(crosstalk)) into the clock traces. 12. t qh = t hp ? t qhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low ( tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers. 13. tdqsq: consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between dqs/ dqs and associated dq in any given cycle. 14. dal = wr + ru{trp(ns)/tck(ns)}, where ru stands for round up . wr refers to the twr parameter stored in the mrs. for trp, if the result of the division is not already an integer, round up to the next highest integer. tck refers to the appl ication clock period. example: for ddr533 at tck = 3.75ns with twr programmed to 4 clocks. tdal = 4 + (15ns/3.75ns) clocks = 4+(4) clocks = 8 clocks. 15. the clock frequency is allowed to change during self?ref resh mode or precharge power-down mode. in case of clock frequency change during prec harge power-down, a specific procedure is required as described in section 2.9. 16. odt turn on time min is when th e device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond. 17. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in hi gh impedance. both are measured from taofd. 18. thz and tlz transitions occur in the same access time as valid data transitions. thesed parameters are referenced to a specific voltage level which specifies when the device ou tput is no longer driving(thz), or begins driving (tlz). below f igure rev. 0.4 / sep. 2006 32 1 1 hy5ps561621a(l)fp shows a method to calculate the point when device is no longer driving (thz), or begins driving (tlz) by measuring the si gnal at two different voltages. the actu al voltage measurement points are not critical as long as the calc ulation is consisten et. 19. trpst end point and trpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (trpst), or begins driving (trpre). belo w figure shows a method to calculate these points when the device is no longer driving (trpst), or begins driving (trpre). below figure shows a method to calculate these points when the devi ce is no longer driving (trpst), or begins driving (trpre) by measuring the sign al at two different vo ltages. the actual vol tage measurement points are not critical as long as the calc ulation is consistent. 20. input waveform timing with differential data strobe enabled mr[bit10] =0, is referenced from the input signal crossing at t he v ih (ac) level to the differential data strobe crosspoint for a rising signal, and fr om the input signal crossing at the v il (ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. 21. input waveform timing with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at th e v ih (dc) level to the differential data strobe crosspoint for a rising signal and v il (dc) to the differential data strobe crosspoint for a falling signal ap plied to the device under test. 22. input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. 23. input waveform timing is referenced from the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under test. thz , trpst end point = 2*t1-t2 tlz , trpre begin point = 2*t1-t2 voh + xmv voh + 2xmv vol + 1xmv vol + 2xmv thz trpst end point vtt + 2xmv vtt + xmv vtt -xmv vtt - 2xmv thz trpre begin point dqs v ddq v ih(ac) min v ih(dc) min tdh tds dqs v ref (dc) v ss v il(dc) max v il(ac) max tdh tds differential input waveform timing rev. 0.4 / sep. 2006 33 1 1 hy5ps561621a(l)fp 24. twtr is at least two clocks (2*tck) independent of operation frequency. 25. input waveform timing with single-ended data strobe enabled mr[bit10] = 1, is referenced from the input signal crossing at the vih(ac) level to the single-ended data strobe crossing vih/l(dc) at the start of its tr ansition for a rising signal, and from t he input sig- nal crossing at the vil(ac) level to the single-ended data strobe crossing vih/l(dc) at the start of its transition for a falli ng signal applied to the device under test. the dqs signal mu st be monotonic between vil(dc)max and vih(dc) min. 26. input waveform timing with single-ended data strobe enabled mr[bit10] = 1, is referenced from the input signal crossing at the vih(dc) level to the single-ended data strobe crossing vih/l(ac) at the end of its transition fo r a rising signal, and from the input sig- nal crossing at the vil(dc) level to the si ngle-ended data strobe crossi ng vih/l(ac) at the end of its transition for a falling signal applied to the device under test. the dqs signal mu st be monotonic between vil(dc) max and vih(dc) min. 27. tcke min of 3 clocks means cke must be registered on three consecutive positive cl ock edges. cke must remain at the valid i nput level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of tis + 2*tck + tih. dqs v ddq v ih(ac) min v ih(dc) min tih tis dqs v ref (dc) v ss v il(dc) max v il(ac) max tih tis rev. 0.4 / sep. 2006 34 1 1 hy5ps561621a(l)fp 5. package dimensions package dimension(x16) 84 ball fine pitch ball grid array outline a1 ball mark 13.00 +/- 0.10 |
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